DATAMATH CALCULATOR MUSEUM
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DATAMATH CALCULATOR MUSEUM |
When Sharp released in October 1969 with the QT-8D the first "small electronic desktop calculator", it was using a chipset of five devices jointly developed with North American Rockwell’s Autonetics division: NRD2256, AC2261, DC2266, AU2271 and the clock driver CG1121. Sharp reused this chipset with the ELSI-8 (EL-8), a compact, battery-operated calculator introduced in November 1970, its offspring ELSI-8A and the QT-8B variation of the QT-8D. An upgraded design of the Rockwell Chipset supported a User Memory function deployed in the battery-operated EL-8M and the EL-160 small electronic desktop calculator.
The massive contract from Sharp, $30 million US$ in 1969 or around $250 million US$ inflation adjusted in 2025, was Rockwell’s entry into the MOS LSI (Metal-oxide Semiconductor Large Scale Integration) business, but the contracts with Sharp covered only delivery of these chips till January 1971. Under an agreement between the two companies, Sharp would manufacture them as soon as in 1971 in Japan with technical assistance from Rockwell – jumpstarting Sharp’s entry as provider for MOS LSI Chips.
Rockwell understood the opportunities of their MOS LSI technology and their experience to mass-produce chips very competitively for consumer electronics and started the design of their own "Standard Building-Block Circuits for Calculators". This set of modular building blocks consisted of four Standard Building Blocks that needed an additional customer-programmed MOS ROM (Read-only Memory) and interfacing logic for the Input (Keyboard) and Output (Display and/or Printer) Interfaces to complete the electronics of a desktop calculator. The architecture of the Building Blocks allowed even for printing or programmable desktop calculators with 10 to 16 digits of capacity and the North American Rockwell Microelectronics Company formally announced on January 13, 1971 the chip set.
The four Standard Building Blocks or Calculator Chips were nick-named C, A, T, and S based on their functionality:
The C Chip
The The C chip serves as master control over other chips in the standard calculator chipset and contains status registers which are used to indicate such conditions as those in which the calculator is in "add" state, has overflowed, or has an error. The C chip senses the status of selected registers, the status of flip-flops or discretes as selected by ROM address, and the status of keyboard inputs such as the decimal point. Using this information, the C chip generates output commands to coordinate the activities of the other calculator chips.The A Chip
The A chip performs decimal calculations. Included on the A chip is circuitry for input/output logic control of the data entered into various registers. Specifically, the A chip contains:
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• A serial decimal adder • A ROM address register • A two-level stack for return address storage • Register status determining logic • X and Y register storage and shift logic • Operand inter-register transfer logic |
The T Chip
The
T chip contains the arithmetic registers and the memory registers.
Specifically, the T chip contains:
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• Storage for four numbers (of length 10, 12, 14, or 16 decimal digits, depending upon the model) in four memory registers • Three 73-bit registers for operands X, Y, and Z • Interfacing logic to a keyboard • An output signal to indicate the maximum decimal point setting permissible on the model |
The S Chip
The S chip contains logic for auxiliary register Z, exponents, and binary logic. It also contains the exponent register and the master time-base generator. Two hard-wired inputs to the S chip cause the time-base generate clocking for word lengths of 10, 12, 14, or 16 digits.
Specifically, the S chip contains:
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• Means to generate timing signals • A binary adder • Seven bits of the Z register and logic for either left-sifting or right-shifting of the contents of Z • The 8-bit exponent registers associated with the operand registers X, Y, and Z • Logic for determining the condition of the Z register and outputting the status • Means to generate the algebraic sign to be used by the decimal adder • Means to generate a "power on" signal |
ROM Circuits
The ROM circuitry implements the microprogram for the set of standard calculator chips. In addition, the ROM contains the 4-phase clock for the calculator.
The ROM is available with three different capacities:
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• 256 Words * 17 Bits • 384 Words * 17 Bits • 512 Words * 17 Bits |
There may be as many as four micro instructions per word.
In a two-ROM configuration, ROM #1 would contain the 4-phase clock and the more
"conventional" instructions. ROM #2 would be used to perform additional functions such as sin, cos, or exponential operators.
Input/Output Chips
Depending upon requirements of the particular calculator system, from one to four input/output interfacing chips are necessary.
Programmability
Additional dynamic storage is required for a programmable calculator. From one to three additional chips are needed for those storage, depending upon the lengths of the program (number of instructions) and the type of instructions which are to be implemented.
Register Expandability
A "TT" chip may be substituted for the T chip, and with the addition of one or two
"M" chips either eight or sixteen independent full registers may be obtained. The TT chip performs register selection for 1-of-16.
Each M chip contains eight memory registers, including decimal point and sign of each word.
As of today, we discovered less than ten designs centered around the C-A-T-S Standard Building-Block Circuits for Calculators and typical designs make use of six or seven PMOS LSI Chips. Coincidence or not, these designs look very, very similar to an earlier chipset with six PMOS LSI Chips used in Sharp’s CS-363 and CS-242 desktop calculators, with observed Date codes as early as November 1970. We assume that "tit for tat" translated in 1970 into::
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• Sharp’s access to Rockwell’s chip design and manufacturing knowhow • Rockwell’s access to Sharp’s calculator logic design knowhow |
QUICK-LINK to
Rockwell Calculator Integrated Circuits.
| Type | Function | Calculators | Keyboard | Digits | Printer | Characters | Special Functions |
| 10177 10178 10179 10180 |
C Chip A Chip T Chip S Chip |
Victor 18-1721, 18-1441, 18-3440, 18-3441 Anita 1211P, 1212D, 1233D Totalia LS14.1 |
[+][−][=] | 8 | |||
| 10182 | Input/Output Chip | Victor 18-1721, 18-1441 | [+][−][=] | 16, 14 | n.a. | n.a. | |
| 10306 10307 |
Input/Output Chips | Victor 18-3440, 18-3441 | [+][−][=] | 16 | Drum | 18 | |
| 10363 | Input/Output Chip | Anita 1211P | [+][−][=] | 12 | Drum | 18 | |
| 10560 | Input/Output Chip | Totalia LS14.1 | [+][−][=] | n.a. | Drum | 18 | |
| 10562 | Input/Output Chip | Anita 1212D, 1233D | [+][−][=] | 12 | n.a. | n.a. | |
| 15000 | ROM Chip | Victor 18-1441 | [+][−][=] | 14 | n.a. | n.a. | [M+][M−][M+=][M−=][MR][MRC][EX][SET] |
| 15003 | ROM Chip | Anita 1212D, 1233D | [+][−][=] | 12 | n.a. | n.a. | |
| 15020 | ROM Chip | Victor 18-3441 | [+][−][=] | 16 | Drum | 18 | |
| 15022 | ROM Chip | Totalia LS14.1 | [+][−][=] | 14 | n.a. | n.a. | |
| 15023 | ROM Chip | Anita 1211P | [+][−][=] | 12 | Drum | 18 | |
| 15027 | ROM Chip | Victor 18-3440 | [+][−][=] | 16 | Drum | 18 | |
| 15320 | ROM Chip | Victor 18-1721 | [+][−][=] | 16 | n.a. | n.a. |
| Description | Comments | |
| Architecture | MOS LSI Chipset | First Generation |
| Category | Register Processor | Similar to PPS-4 |
| Related | ||
| ROM Size | 4,352 Bits 6,528 Bits 8.704 Bits |
256 Words * 17 Bits 384 Words * 17 Bits 512 Words * 17 Bits |
| RAM Size | t.b.d. Bits | |
| Outputs | Per Input/Output Chips | |
| Inputs | Per Inout/Output Chips |
The Datamath Calculator Museum DCM-50A (Platform) was designed for single-chip calculators and does not support the Rockwell C-A-T-S Standard Building Blocks.
The C-A-T-S Standard Building Blocks were manufactured in a 15 um metal gate PMOS process.
The die size of the C chip is approximately 150 mils * 150 mils / 3.8 mm * 3.8 mm and implements 240 logical equations.
The die size of the A chip is approximately 160 mils * 160 mils / 4.0 mm * 4.0 mm and implements 250 logical equations.
The die size of the T chip is approximately 150 mils * 160 mils / 3.8 mm * 4.0 mm and implements 200 logical equations.
The die size of the S chip is approximately 140 mils * 160 mils / 3.6 mm * 4.0 mm and implements 250 logical equations.
The C-A-T-S Standard Building Blocks are using a standard 0.9” wide 42-pin QIP (Quad In-line Package with a staggered 0.1” / 2.54 mm lead pitch) with ceramic or plastic body and metal lids.
Calculators based on the C-A-T-S Standard Building Blocks typically make use of 12-digit to 16-digit displays and/or 18-character printers.
If you have additions to the above datasheet please email: joerg@datamath.org.
© Joerg Woerner, March 1, 2025. No reprints
without written permission.