DATAMATH CALCULATOR MUSEUM
When Texas Instruments started in Summer 1979 working on the "Project X" leading to the TI Programmable 88 with a clear objective to provide an upgrade leadership product to replace the TI-59, one of the earliest requirements established was the transition from a power-hungry 7-segment LED display to a full alphanumeric LC-Display with sixteen characters of a 5*7 dot matrix, each. Understanding the high number of electric connections necessary between the column and row drivers and the LC-Display and the pin count limitations of traditional DIP (Dual Inline Package) encapsulations, TI decided:
• Divide the 16 characters alphanumeric LC-Display into two halves of 8 characters
• Break the 40-pin barrier of DIP packages with using Chip-on-Board (COB) technology
The TP0530 Cascadable Display Drivers integrates the following functional blocks:
• 64-bit Data Register to store 8 characters
• Character Generator ROM with 4,480 Bits capacity for 128 characters in 5*7 dot matrix representation
• Row Address Generator for 7 rows
• 280-bit Shift Register holding 7 rows of 8 characters with 5 Segments, each
• 40-bit Segment Latch for 8 characters with 5 Segments, each
• 40 Column Drivers for 8 characters with 5 Segments, each
• 7 Row Drivers (Commons)
• 3-bit Flags Register to store 8 Display Indicators
• Flag Generator ROM with 56 Bits capacity for 8 Display Indicators
• 1-bit Segment Latch for Display Indicators
• 1 Column Driver for Display Indicators
• Temperature compensation for the LC-Display
Cascading multiple TP0530 chips (two in case of the TI-88, its only known application) is accomplished by 3 different means:
• Each TP0530 features a Data In and Data Out pad to daisy-chain the chips
• Each TP0530 features a Data Clock In and Data Clock Out pad to daisy-chain the chips
• A M/S pad defines the Master chip generating the Row scanning of the LC-Display
|TP0530-M||TI Programmable 88||Cascadable Display Driver||Master
Rightmost 8 characters
|TP0530-S||TI Programmable 88||Cascadable Display Driver||Slave
Leftmost 8 characters
The TP0530 is manufactured in a 5 um silicon gate CMOS process (metal width = 0.20 mil / 5.0 um, metal spacing = 0.20 mil / 5.0 um, diffusion width = 0.20 mil / 5.0 um, diffusion spacing = 0.20 mil / 5.0 um).
The die size of the TP0530 is approximately 215 mils * 215 mils / 5.4 mm * 5.4 mm.
The TP0530 has 71 bonding pads and uses Chip-on-Board (COB) technology. In the TI-88 calculator the display assembly uses two individual printed circuit boards (PCBs) for the 8 rightmost characters (Master) and 8 leftmost characters (Slave). The TP0530 on the Master-PCB is connected with 60 wires and the TP0530 on the Slave-PCB with 56 wires to the respective traces on the PCB.
If you have additions to the above datasheet please email: email@example.com.
© Sean Riddle and Joerg Woerner, January 22, 2022. No reprints
without written permission.