Texas Instruments TI-Nspire (Design Validation Tests 1.2)

Date of introduction:  (never) Display technology:  LCD dot matrix
 16-level greyscale
New price:   Display size:  240 * 320 pixels 
Size:  7.9" x 3.9" x 0.85"
 200 x 100 x 22 mm3
Weight:  9.8 ounces, 278 grams Serial No:  P3-ASIC-DVT1.2 0318
Batteries:  4*AAA Date of manufacture:  mth 02 year 2007
AC-Adapter:   Origin of manufacture:  China (S)
Precision:  14 Integrated circuits:  CPU: TI-NS2006A (L9A0702)
 SDRAM: HYB18L256160
 Flash: SST 39WF400A, ST NAND256R3A
 Display: Novatek NT7702H, 2*xxx
Program steps:  22M Bytes, 512k Bytes Flash-ROM Courtesy of:  Joerg Woerner 

We noticed rumors in the graphing calculator community about an upcoming product from Texas Instruments around June 2006 and it was obvious that they not refer to the PET project. It took about 6 month and the first images of the TI-Nspire CAS+, also known as Phoenix 1, appeared in different forums on the Internet. These prototypes of the later TI-Nspire CAS were used in different field tests all over the world and some of them found their way to collectors.

We assume that Texas Instruments manufactured more than 1000 samples of the TI-Nspire CAS+ for evaluation purposes. Field tests were reported from Germany, Switzerland and New Zealand. As a result of these extensive tests we learned 2 major changes in the design and concept of the calculator till its official introduction in July 2007 (Europe) and September 2007 (USA):

The TI-Nspire with its snap-in TI-84 Plus Keypad was added to the TI-Nspire CAS
The internal architecture was optimized with respect to manufacturing costs
    and power consumption

And how does this TI-XXXXXXXXXXX fit into the evolution of the TI-Nspire?

The most important detail: It is a prototype of the TI-Nspire, not the TI-Nspire CAS!



Serial No

Date of manufacture


Design Verification Tests

P3-ASIC-DVT1.2 0318

Feb. 2007


Mass Production


May 2007

Unfortunately gives the back of the calculator no hint about the date of manufacture and therefore we dismantled it. The serial number “P3-ASIC-DVT1.2 0318” of this TI-Nspire prototype suggested already the use of the ZEVIO architecture known from the final products but the date code "0635 - year 2006, week 35" surprised us. Based on the fact that Texas Instruments manufactured even in October 2006 the TI-Nspire CAS+ Prototypes still based on the TI-OMAP NP31AZZG architecture this find is difficult to understand. Dealing with a very long lead-time for the design of an ASIC with the complexity of the ZEVIO we assume a pretty early project start for the non-Cas version of the TI-Nspire. The printed circuit boards (PCB's) of the TI-Nspire prototype carry a label "0703 - probably for year 2007, week 03" which could indicate a manufactureing date of the calculator around February 2007.

Don't miss the TI-XXXXXXX, you are right: 11 X vs 7 X.

Architecture: Dismantling the TI-XXXXXXXXXXX (a.k.a. TI-Nspire Prototype) reveals a modern architecture based on the ZEVIO architecture introduced by LSI Logic early in 2006. The ZEVIO architecture is ideally suited for consumer electronics products such as GPS navigation systems, electronic toys and edutainment applications, personal media players, and handheld products. The System-on-Chip (SoC) approach of the ZEVIO is centered around Intellectual Property blocks from ARM (e.g. the 90 MHz ARM9 32-bit RISC processor), LSI Logic's 200-MHz 16-bit ZSP-400 Digital Signal Processor, 16-bit SDRAM memory controller, NAND flash memory controller, USB-2.0 (including USB On the Go), IEEE 1394 Firewire, and Secure Digital I/O and a LCD controller for TFT displays. We noticed this approach already with the PLT-SHH1 prototype based on the sophisticated POMAP1509E, a design based on the OMAP™1510 series dual-core processor.

The chips with the TI-NS20xx / L9Axx identification are designed in a 0.13um process and manufactured in any of LSI Logic's foundries, which include Semiconductor Manufacturing International, Taiwan Semiconductor Manufacturing and United Microelectronics.

Including the TI-Nspire and TI-Nspire CAS calculators from the actual production in May resp. April 2006 we observed 3 different ASIC identifiers:




Date Code




wk 35 year 2006

TI-Nspire CAS

Final product


wk 05 year 2007


Final product


wk 14 year 2007

We learned from other ASIC designs that LSI Logic is assigning the L9Axxxx number in a sequential order. This suggests that the TI-Nspire CAS ASIC was designed first but is already in a Revision -1 while the design of the TI-Nspire ASIC was started later.

Memory: The TI-Nspire makes use of three different memory chips:


Flash memory is non-volatile and does not need a battery to maintain the information stored in the chip. In the past years two different technologies emerged in parallel with some advantages and disadvantages.

The NOR Flash-ROM was invented by Toshiba in 1984 and found its way immediately as a replacement of the more expensive ROM (NRE mask costs) and EEPROM (device costs) memory. The NOR Flash-ROM's use an address and data bus to allow the random access to any memory location. Main disadvantages of the NOR Flash-ROM compared to the NAND Flash-ROM are the higher costs, larger housings and slower write speeds.

The disassembled TI-Nspire Prototype (Manufactured around February 2007) makes use of one SST 39WF400A, manufactured by Silicon Storage Technology, Inc. with a a 256k*16 organization. Please keep in mind that even the TI-89 Titanium used 2M*16 Flash-ROM.

The NAND Flash-ROM architecture was introduced by Toshiba in 1989 and is based on pages of typically 512 to 2048 Bytes and blocks of typical 32 or 64 pages.

While programming is performed on a page basis, erasure can only be performed on a block basis. NAND Flash-ROM's requires bad block management to be performed by device driver software or hardware. Due to the missing address bus the NAND Flash-ROM chip doesn't allow random access to the individual memory positions and therefore it can't be used for program memory of a microprocessor. Typical use of the NAND Flash-ROM memory is file based mass-memory storage such as memory cards.

The disassembled TI-Nspire Prototype makes use of one ST NAND256R3A NAND Flash-ROM with 32M Bytes size.

SDRAM is the abbreviation of synchronous dynamic random access memory and is used as program and data memory for microprocessor systems. Each bit of data in a SDRAM is stored in separate condensator on the integrated circuit. Since these capacitors leak charge, the information eventually fades unless the capacitor charge is refreshed periodically.

Because of this refresh requirement, it is a dynamic memory as opposed to SRAM and other static memory. Its advantage over SRAM is its structural simplicity: only one transistor and a capacitor are required per bit, compared to six transistors in SRAM. This allows SDRAM to reach very high density at low cost. Since SDRAM loses its data when the power supply is removed, it is accompanied usually by a NOR Flash memory.

During power-up of the system the program content of the NOR Flash is simply copied into the SDRAM and executed from there. We assume that the TI-Nspire uses the SDRAM as workspace for user data but stores changes on them into the NAND Flash memory.

The disassembled TI-Nspire Prototype makes use of one Qimonda HYB18L256160 SDRAM with 16M*16 size.

Display: The TI-Nspire uses a high-contrast display with a resolution of 240 * 320 pixels, a huge improvement over the TI-89 Titanium with 100 * 160 pixels or the Voyage 200 with 128 * 240 pixels. The large 16-level greyscale display includes a novel split screen capability with up to 4 views.



TI-Nspire_P_K_OS.jpg (91676 Byte)TI-Nspire_P_OS.jpg (96468 Byte)1.1.9227 (May 15, 2007)  
Boot1 Code Version: 1.1.9170
Boot2 Code Version: 1.1.9170
TI-84 Plus Silver Edition 2.42

1.2.2398 (August 30, 2007

You can check the ROM version of your TI-Nspire using the following key sequence and reading the number on your screen:

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Information provided by Xavier Andréani. 

TI-Nspire Computer Link Software for Windows



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© Joerg Woerner, February 18, 2008. No reprints without written permission.