DATAMATH CALCULATOR MUSEUM
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DATAMATH CALCULATOR MUSEUM |
Fairchild Semiconductor developed early in the 1970s a family of micro-programmed MOS/LSI (Metaloxide Semiconductor/Large Scale Integration) processor blocks called PPS 25 (Programmed Processor System - 25 Digits) to bridge the gap between simple electronic calculators and microcomputers. A minimal PPS 25 design uses six Micromosaic chips interconnected by 4-bit data buses and various control signals, corresponding directly to the block diagram of a computer based on the Harvard architecture.
At the core of the system is the CPU, composed of the 3805 Arithmetic/Logic Unit and the 3806 Control Unit. The 3808 and 3809 Data Memories each provide three dynamic 25-digit shift registers, while the 3810 Program Memory provides 256 Words * 12 Bits of storage. The 3803 and 3807 Input Device chips support up to 32 keys and 16 switches each, and the 3811 Output Device drives displays of up to 16 Digits.
The 3805 Arithmetic Chip contains the Adder/Subtractor and a 25-digit memory register. The 3805 chip, along with auxiliary 3808 and 3809 Memory Registers, receive micro-instructions from the 3810 ROM (Read-Only Memory) chips. The micro-instructions contain a data source address, a data result destination address, and an operation code. The instructions allow additions, subtractions, or transfers to take place between registers. Incrementing, decrementing, complementing, and clearing of any of the seven registers and other operations can also be performed. Data can be entered either externally or created internally by the use of a "load immediate" instruction.
The 3805 Arithmetic Chip is combining the following features in one 18-pin package:
4-bit Input Data Bus X0-X3
4-bit Output Data Bus Y0-Y3
Instruction Decoder
4-Bit BCD Adder
25-digit BCD Register A
Register Selection Logic
Interface to 3806 Function and Timing UnitQUICK-LINK to PPS 25 Building Blocks.
Type Year Function Products Comments 3805 1973 Arithmetic Chip Centurion Industries Multiputer CPD-15, CPD-35
Cybernetic Systems Mathiputer CPD-15, CPD-3518 pin Ceramic DIP
Description Comments Architecture Harvard, Processor Blocks First Generation Category Register Processor 25-digit BCD-serial ROM Size not applicable RAM Size 150 Bits 1 Register * 100 Bits (25 Digits)
2 Registers * 25 Bits
Item Min Typ Max Unit Comments VSS 4.75 5.0 5.25 V TTL, DTL compatible VDD 0 V VGG -9.5 -10.0 -10.5 V VOH1 2.4 VSS V 1 TTL Load VOL1 0 0.4 V 1 TTL Load VOH2 VSS-1.0 VSS V MOS Load VOL2 0 0.5 V MOS Load VIH1 VSS-1.0 VSS V DTL/TTL compatible VIL1 VDD VSS-4.2 V DTL/TTL compatible VIH2 VSS-1.0 VSS V Clock Input VIL2 VGG VSS-14.0 V Clock Input Ext. CK 400 kHz Two-phase clock CP1 Width us Active low CP2 Width us Active low CP1 to CP2 Delay us Between pulses
The 3805 Arithmetic Chip uses a standard 0.3 wide 18-pin CDIP (Ceramic Dual In-line Package with a 0.1 / 2.54 mm lead pitch).
The die of the 3805 Arithmetic Chip is attached to the gold-plated cavity of the 16-pin CDIP with its Pin 3 (VSS) bonded to the substrate and silicon die.
The PPS 25 Building Blocks were manufactured in a 11.5 um metal gate PMOS process (metal width = 0.45 mil / 11.5 um, metal spacing = 0.44 mil / 11.5 um, diffusion width = 0.30 mil / 8.0 um, diffusion spacing = 0.30 mil / 8.0 um). The die size of the 3805 Arithmetic Chip is approximately 150 mils * 140 mils / 3.8 mm * 3.5 mm.
PPS 25 - 3805 Arithmetic Chip Pin IO Function Pin IO Function 1 O Data Bus Y3 18 O Data Bus Y2 2 I Data Bus X3 17 O Data Bus Y1 3 V Positive Voltage VSS 16 O Data Bus Y0 4 I Data Bus X2 15 I Time Enable ROM 5 I Data Bus X1 14 O Adder FLAG 6 I Data Bus X0 13 I SYNC 7 V Common Voltage VDD 12 O Adder BOROW 8 I Clock P2 11 I Micro Instruction Input 9 V Negative Voltage VGG 10 I Clock P1
If you have additions to the above datasheet please email: joerg@datamath.org.
© Joerg Woerner, May 8, 2026. No reprints
without written permission.