DATAMATH CALCULATOR MUSEUM
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DATAMATH CALCULATOR MUSEUM |
Fairchild Semiconductor developed early in the 1970s a family of micro-programmed MOS/LSI (Metaloxide Semiconductor/Large Scale Integration) processor blocks called PPS 25 (Programmed Processor System - 25 Digits) to bridge the gap between simple electronic calculators and microcomputers. A minimal PPS 25 design uses six Micromosaic chips interconnected by 4-bit data buses and various control signals, corresponding directly to the block diagram of a computer based on the Harvard architecture.
At the core of the system is the CPU, composed of the 3805 Arithmetic/Logic Unit and the 3806 Control Unit. The 3808 and 3809 Data Memories each provide three dynamic 25-digit shift registers, while the 3810 Program Memory provides 256 Words * 12 Bits of storage. The 3803 and 3807 Input Device chips support up to 32 keys and 16 switches each, and the 3811 Output Device drives displays of up to 16 Digits.
The 3808 Memory Register is providing three auxiliary 25-digit BCD Register B, C, and D for the PPS 25 System and the 3808 Memory Register is providing three auxiliary 25-digit BCD Register E, F, and G for the PPS 25 System.
The 3808/3809 Memory Register chips are combining the following features in one 16-pin package:
4-bit Input Data Bus X0-X3
4-bit Output Data Bus Y0-Y3
Instruction Decoder
25-digit BCD Registers B, C, and D (3808)
25-digit BCD Registers E, F, and G (3809)QUICK-LINK to PPS 25 Building Blocks.
Type Year Function Products Comments 3809 1973 Memory Register Centurion Industries Multiputer CPD-15, CPD-35
Cybernetic Systems Mathiputer CPD-15, CPD-3516 pin Ceramic DIP
Item Min Typ Max Unit Comments VSS 4.75 5.0 5.25 V TTL, DTL compatible VDD 0 V VGG -9.5 -10.0 -10.5 V VOH1 2.4 VSS V 1 TTL Load VOL1 0 0.4 V 1 TTL Load VOH2 VSS-1.0 VSS V MOS Load VOL2 0 0.5 V MOS Load VIH1 VSS-1.0 VSS V DTL/TTL compatible VIL1 VDD VSS-4.2 V DTL/TTL compatible VIH2 VSS-1.0 VSS V Clock Input VIL2 VGG VSS-14.0 V Clock Input Ext. CK 400 kHz Two-phase clock CP1 Width us Active low CP2 Width us Active low CP1 to CP2 Delay us Between pulses
The 3809 Memory Register uses a standard 0.3 wide 16-pin CDIP (Ceramic Dual In-line Package with a 0.1 / 2.54 mm lead pitch).
The die of the 3809 Memory Register is attached to the gold-plated cavity of the 16-pin CDIP with its Pin 2 (VSS) bonded to the substrate and silicon die.
The PPS 25 Building Blocks were manufactured in a 11.5 um metal gate PMOS process (metal width = 0.45 mil / 11.5 um, metal spacing = 0.44 mil / 11.5 um, diffusion width = 0.30 mil / 8.0 um, diffusion spacing = 0.30 mil / 8.0 um). The die size of the 3809 Memory Register is approximately 110 mils * 155 mils / 2.8 mm * 4.0 mm.
PPS 25 - 3808/3809 Memory Register Pin IO Function Pin IO Function 1 O Data Bus X0 16 O Data Bus X1 2 V Positive Voltage VSS 15 I Data Bus Y1 3 V Negative Voltage VGG 14 I Data Bus Y3 4 V Common Voltage VDD 13 O Data Bus X3 5 I Data Bus Y0 12 I Micro Instruction
Input MI6 I Data Bus Y2 11 O Data Bus X2 7 I SYNC 10 I Clock P1 8 I Time Enable ROM 9 I Clock P2
If you have additions to the above datasheet please email: joerg@datamath.org.
© Joerg Woerner, May 8, 2026. No reprints
without written permission.