DATAMATH CALCULATOR MUSEUM
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DATAMATH CALCULATOR MUSEUM |
Fairchild Semiconductor developed early in the 1970s a family of micro-programmed MOS/LSI (Metaloxide Semiconductor/Large Scale Integration) processor blocks called PPS 25 (Programmed Processor System - 25 Digits) to bridge the gap between simple electronic calculators and microcomputers. A minimal PPS 25 design uses six Micromosaic chips interconnected by 4-bit data buses and various control signals, corresponding directly to the block diagram of a computer based on the Harvard architecture.
At the core of the system is the CPU, composed of the 3805 Arithmetic/Logic Unit and the 3806 Control Unit. The 3808 and 3809 Data Memories each provide three dynamic 25-digit shift registers, while the 3810 Program Memory provides 256 Words * 12 Bits of storage. The 3803 and 3807 Input Device chips support up to 32 keys and 16 switches each, and the 3811 Output Device drives displays of up to 16 Digits.
The 3810 ROM (Read-Only Memory) contains a mask-programmable 256 * 12 Bits Micro Instruction Memory, up to 26 3810 ROMs can be used in a PPS 25 System for a combined 3,328 Micro Instruction Words. All 3810 ROMs in a PPS 25 System receive an 8-bit address simultaneously and the selected 3810 ROM shifts out the selected 12-bit instruction. Data stored in the ROMs can be transferred to the accumulator of the 3805 Arithmetic Chip to generate constants or addresses.
The 3810 ROM is combining the following features in one 16-pin package:
Serial Micro Instruction Input MI
Serial Micro Instruction Output MIO
Address Decoder
ROM Select Logic
256 * 12 Bits mask-programmable Micro Instruction MemoryQUICK-LINK to PPS 25 Building Blocks.
Type Year Function Products Comments 3810 (SL30745) 1973 ROM Centurion Industries Multiputer CPD-15, CPD-35
Cybernetic Systems Mathiputer CPD-15, CPD-3516 pin Ceramic DIP
Item Min Typ Max Unit Comments VSS 4.75 5.0 5.25 V TTL, DTL compatible VDD 0 V VGG -9.5 -10.0 -10.5 V VOH1 2.4 VSS V 1 TTL Load VOL1 0 0.4 V 1 TTL Load VOH2 VSS-1.0 VSS V MOS Load VOL2 0 0.5 V MOS Load VIH1 VSS-1.0 VSS V DTL/TTL compatible VIL1 VDD VSS-4.2 V DTL/TTL compatible VIH2 VSS-1.0 VSS V Clock Input VIL2 VGG VSS-14.0 V Clock Input Ext. CK 400 kHz Two-phase clock CP1 Width us Active low CP2 Width us Active low CP1 to CP2 Delay us Between pulses
The 3810 (SL30745) ROM uses a standard 0.3 wide 16-pin CDIP (Ceramic Dual In-line Package with a 0.1 / 2.54 mm lead pitch).
The die of the 3810 (SL30745) ROM is attached to the gold-plated cavity of the 16-pin CDIP with its Pin 3 (VSS) bonded to the substrate and silicon die. Pins 1, 2, 6, 8, 9, 10, 11, and 16 are not bonded to the silicon die.
The PPS 25 Building Blocks were manufactured in a 11.5 um metal gate PMOS process (metal width = 0.45 mil / 11.5 um, metal spacing = 0.44 mil / 11.5 um, diffusion width = 0.30 mil / 8.0 um, diffusion spacing = 0.30 mil / 8.0 um). The die size of the 3810 (SL30745) ROM is approximately 115 mils * 135 mils / 2.9 mm * 3.5 mm.
PPS 25 - 3810 (SL30745) ROM Pin IO Function Pin IO Function 1 N.C. 16 N.C. 2 N.C. 15 I SYNC 3 V Positive Voltage VSS 14 I Clock P1 4 I Micro Instruction
Input MI13 V Negative Voltage VGG 5 O Micro Instruction
Output MIO12 I Clock P2 6 N.C. 11 N.C. 7 V Common Voltage VDD 10 N.C. 8 N.C. 9 N.C.
If you have additions to the above datasheet please email: joerg@datamath.org.
© Joerg Woerner, May 8, 2026. No reprints
without written permission.