DATAMATH CALCULATOR MUSEUM
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DATAMATH CALCULATOR MUSEUM |
Fairchild Semiconductor developed early in the 1970s a family of micro-programmed MOS/LSI (Metaloxide Semiconductor/Large Scale Integration) processor blocks called PPS 25 (Programmed Processor System - 25 Digits) to bridge the gap between simple electronic calculators and microcomputers. A minimal PPS 25 design uses six Micromosaic chips interconnected by 4-bit data buses and various control signals, corresponding directly to the block diagram of a computer based on the Harvard architecture.
At the core of the system is the CPU, composed of the 3805 Arithmetic/Logic Unit and the 3806 Control Unit. The 3808 and 3809 Data Memories each provide three dynamic 25-digit shift registers, while the 3810 Program Memory provides 256 Words * 12 Bits of storage. The 3803 and 3807 Input Device chips support up to 32 keys and 16 switches each, and the 3811 Output Device drives displays of up to 16 Digits.
The 3811 Output Device contains the necessary latches for receiving, storing, and transmitting the BCD representation of a character. A position counter provided an output code for 1 of 16 positions, necessary to multiplex up to 16 display elements. Decimal point, sign, and general purpose programmed flag outputs are also provided.
The 3811 Output Device is combining the following features in one 24-pin package:
4-bit Input Data Bus Y0-Y3
4-bit Digit Select A0-A3
4-bit BCD Data Output K0-K3
Three Outputs Decimal Point, Sign, Memory
16-digit BCD Data Register
Serial Micro Instruction Input MI
Leading Zero Suppression
Display BlankingQUICK-LINK to PPS 25 Building Blocks.
Type Year Function Products Comments 3811 1973 Output Device Centurion Industries Multiputer CPD-15, CPD-35
Cybernetic Systems Mathiputer CPD-15, CPD-3524 pin Ceramic DIP
Item Min Typ Max Unit Comments VSS 4.75 5.0 5.25 V TTL, DTL compatible VDD 0 V VGG -9.5 -10.0 -10.5 V VOH1 2.4 VSS V 1 TTL Load VOL1 0 0.4 V 1 TTL Load VOH2 VSS-1.0 VSS V MOS Load VOL2 0 0.5 V MOS Load VIH1 VSS-1.0 VSS V DTL/TTL compatible VIL1 VDD VSS-4.2 V DTL/TTL compatible VIH2 VSS-1.0 VSS V Clock Input VIL2 VGG VSS-14.0 V Clock Input Ext. CK 400 kHz Two-phase clock CP1 Width us Active low CP2 Width us Active low CP1 to CP2 Delay us Between pulses
The 3811 Output Device uses a standard 0.6 wide 24-pin CDIP (Ceramic Dual In-line Package with a 0.1 / 2.54 mm lead pitch).
The die of the 3811 Output Device is attached to the gold-plated cavity of the 24-pin CDIP with its Pin x (VSS) bonded to the substrate and silicon die.
The PPS 25 Building Blocks were manufactured in a 11.5 um metal gate PMOS process (metal width = 0.45 mil / 11.5 um, metal spacing = 0.44 mil / 11.5 um, diffusion width = 0.30 mil / 8.0 um, diffusion spacing = 0.30 mil / 8.0 um). The die size of the 3811 Output Device is approximately 130 mils * 95 mils / 3.3 mm * 2.4 mm.
PPS 25 - 3811 Output Device Pin IO Function Pin IO Function 1 O Digit Select A1 24 O Digit Select A2 2 O Digit Select A0 23 O Digit Select A3 3 I Clock P1 22 O Decimal Point DP 4 V Negative Voltage VGG 21 O Memory Output M 5 I Clock P2 20 O Minus Sign S 6 V Common Voltage VDD 19 O BCD Data K3 7 I Micro Instruction
Input MI18 O BCD Data K2 8 I Timing Enable ROM 17 O BCD Data K1 9 I SYNC 16 O BCD Data K0 10 V Positive Voltage VSS 15 O Blank Enable BN 11 I Data Bus Y0 14 I Data Bus Y3 12 I Data Bus Y1 13 I Data Bus Y2
If you have additions to the above datasheet please email: joerg@datamath.org.
© Joerg Woerner, May 8, 2026. No reprints
without written permission.