Texas Instruments TP0532

• Features

Texas Instruments introduced on May 24, 1977 the now legendary TI Programmable 59 and its sibling TI-58, featuring a novelty, the Solid State Software Modules™ with up to 5,000 program steps. A small lid on the backside of the TI-58/TI-59 allowed for easy access to the modules roughly the size of thumb tip.

The Master Library, known as "Module -1-", with 25 different programs was included with the TI-58 and TI-59. Twelve additional Solid State Software Modules™, known as "Module -2- to -13-" were available from Texas Instruments as Standard Libraries. Due to this innovative module concept both the TI-58 and TI-59 gained a lot of attention and dozens of Modules were released for applications ranging from insurance fee calculations to tax calculations to screw joint calculations, HVAC design, pool water analysis and even flight computers for the USMC Harrier.

Each of these Modules contains a Mask-ROM (Read-only Memory programmed during the manufacturing process) in a small 8-pin package connected serially to the TMC0500 Building Blocks used with the TI-58/TI-59 and introduced already in 1974 with the SR-50 calculator. While the 13-bit instructions for the TMC0501 Arithmetic chip are stored in SCOM (Scanning and 1k*13-bit Read-only Memory), DSCOM (SCOM with 2.5k*13-bit ROM), or BROM (Bare ROM with 1k*13-bit, no scanning) chips, are user programs stored as OP-Codes or "merged keystrokes" encoded in two BCD (Binary Coded Decimal) digits for a combined 8-bit data size. Storing user data is accomplished by concatenating eight program steps into one data register. Keystroke programmable calculators based on the TMC0500 architecture like the SR-52 and SR-56 store user programs and user data in PRAM (Program Random-access Memory) chips with a capacity of 1,920 bits or 240 program steps/30 data registers accessed through a 4-bit I/O bus.

When Texas Instruments started in Summer 1979 working on the "Project X" leading to the TI Programmable 88 with a clear objective to provide an upgrade leadership product to replace the TI-59, it was decided to take the successful Solid State Software Modules concept two steps ahead, providing:

• Solid State Software approach (CROM) has been expanded to include Drop-in RAM (CRAM)
• CROMs and CRAMs are interchangeable and two slots are available on the calculator
• Basic memory can be expanded to 3,000 steps of 375 data registers
• CROMs will be 15,000 program steps, up to 99 programs per CROM, up to 10,000 steps per program

With the TI-88 based on two 4-bit TP0485 Microcontrollers with integrated Instruction ROM, Texas Instruments consequently used the bidirectional 4-bit I/O bus not only for processor-to-processor communication but to access the various memory chips, too.

The final design of the TI-88 – before it was cancelled in September 1982 – makes use of:

• 2*TP0531 On-board Read/Write Memories with a capacity of 4,800 Bits, each for a combined
   960 program steps/120 data registers available for the user
• TP0532 (CD5402) On-board Read Only Memory with a capacity of 120,000 Bits or 15,000 program steps
• CRAM Plug-in Memory with 2*TP0531 Read/Write Memory with a capacity of 4,800 Bits, each
   for a combined 1,184 program steps/148 data registers available for the user
• CROM Plug-in Memory with TP0532 Read Only Memory with a capacity of 120,000 Bits or 15,000 program steps

The on-board CROM of the TI-88 uses a TP0532 chip with the marking CD5402, the Master Library or "Module -1-" provided with the TI-88 calculator uses a TP0532 chip with the marking CD5403. The CD5401 chip wasn’t discovered as of January 2021.

The TP0532 ROM uses like its predecessor TMC0540 a BCD (Binary Coded Decimal) architecture:

• TMC0540: 5,000*8 Bits capacity, 1-bit data access, 4-digit BCD address (0000-4999), two BCD digits Op-Codes
• TP0532: 15,000*8 Bits capacity, 4-bit data access, 5-digit BCD address (00000-14999), two 4-bit digits (nibbles) Op-Codes

The TP0532 supports four commands to access its data in 4-bit nibbles:

CS IO8 IO4 IO2 IO1 Command Description
0 X X X X DESELCTED Chip Select, Active High
1 0 0 0 0 NOP Chip Selected, Idle
1 1 0 0 1 LOAD ADDRESS Sets memory address pointer to 5-digits BCD value, LSD first with 00000 to 99941
1 1 0 1 0 READ ADDRESS Reads current memory address pointer as 5-digits BCD value, LSD first
1 1 0 1 1 READ 2 DIGITS Reads 2 nibbles and increments address by 1,
Low nibble first
1 1 1 0 0 READ 16 DIGITS Read 16 nibbles and increments address by 8,
Low nibble first per Byte

• Family Members and Applications

Type Calculator Application Comments
TI Programmable 88 System CROM TI-88 Prompting User Interface
TI Programmable 88 Plug-In CROM Module 1 Master Library

• Technical Specifications

Item Min Typ Max Unit Comments
VCC   3.0   V   
GND   0   V   
CK   1,600   kHz  External clock
TACC   2.5   uS  4 States per Command

• Technology

The TP0532 is manufactured in a tbd um metal gate CMOS process.

The die size of the TP0532 is approximately 230 mils * 205 mils / 5.9 mm * 5.2 mm.

• Packaging

The TP0532 uses a 0.4” wide 28-pin SPDIP (Shrink Plastic Dual In-line Package with a 0.07” / 1.778 mm lead pitch).

• Pin Configuration

Pin IO Function Pin IO Function
1   n.c. 28   n.c.
2 V GND 27   n.c.
3   n.c. 26   n.c.
4   n.c. 25   n.c.
5 I CS 24   n.c.
6   n.c. 23   n.c.
7 IO IO8 22   n.c.
8 IO IO4 21   n.c.
9 IO IO2 20   n.c.
10 IO IO1 19   n.c.
11 V VCC Positive Voltage 18   n.c.
12   n.c. 17   n.c.
13 V VCC2 Connect to GND 16   n.c.
14   n.c. 15   n.c.


If you have additions to the above datasheet please email:

© Sean Riddle and oerg Woerner, January 22, 2021. No reprints without written permission.