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Texas Instruments introduced in 1973 with the TI-4000 Desktop calculator a very compact, yet capable product with a 12-digit display as an upgrade option to the TI-3000 and TI-3500 calculators with 8-digit resp. 10-digit displays. The TI-4000 was one of the first applications of TI’s TMS0200 Building Blocks for Desktop Calculators, a groundbreaking architecture centered around a Data Chip and various Support ICs:

• TMS0200 Data Chip – Register Processor with four 16-digit Registers and seven Keyboard Scan inputs • TMS0300 ROM Chip – 512*13 Bits Instruction Memory with serial interface to Data Chip and 13-digit display and keyboard scanning, up to 4 ROM Chips • TMC0400 ROM/Register Chip - 512*13 Bits Instruction Memory with parallel interface to ROM Chip and two 16-digit Registers • TMS0220 Printer Chip – Interface to two-color Drum Printer Mechanism • TMC0250 Printer/Display Chip – Interface to Thermal Printer Mechanism and Dot-Matrix Display

The TMS0200 Data Chip requires in a minimum configuration – as used in the TI-4000 – a TMS0300 ROM Chip for Program Memory and to scan up to 13 digits of the display.

The TMS0200 is based on the Register Architecture of the TMS0100 single-chip calculator circuit design introduced in September 1971 but expands its Serial-Access Memory from 3 Registers * 13 digits to 4 Registers * 16 digits, outsources the 320*11 Bits Program Memory and display scanning to a TMS300 ROM Chip with a capacity of 512*13 Bits and 13 digits scan outputs and abandons the integrated segment decoder.

Communication between the TMS0200 Data Chip and the other family members of the TMS0200 Building Blocks is realized with multiple means:

• 4 S-Times Outputs SA, SB, SC, and SD to signal the 16 States of the Instruction Cycle and synchronize Digit Scanning between the TMS0300 ROM Chip (11 digits D2 – D12) and TMS0200 Data Chip (4 digits D1, D13 – D15) • IRG A and IRG B Inputs to receive the 13-bit Instruction Words from the TMS0300 ROM in two chunks of 6 bits (IRG A B0 – B5) and 7 bits (IRG B B6 – B12) • 4-bit bidirectional I/O Bus I/O 8, I/O 4, I/O 2, and I/O 1 to communicate with the never introduced 10-Register Chips, the two 16-digit Registers of the TMC0400 ROM/Register Chips or the TMS0220 Printer Chip.    Note: The ROM section of the TMC0400 is fed through its 13-bit parallel connection with the TMS0300 to the TMS0200 • CONA Output: Inhibit Increment ROM (Interrupt sequence) • CONB Output: Idle Condition of Data Chip (Idle = Display Mode) • COND Output: Condition Flag • FLG A Output to transmit the Flag register serially • PREG Output: P Register Data Chip addresses ROM • /STB Output as a programmable signal based of D-Times (Display Times, scanning digits) • BUSY Input for slow devices like the Printer Chip

The combination of both its programmability and scalability of the TMS0200 Building Blocks for Desktop Calculators allowed the introduction of some interesting products like the Hexadecimal Calculator/Converter SR-22 bypassing the BCD correction of the ALU (Arithmetic Logic Unit) or the massive Printing Desktop calculator TI-620.

While none of the known products based on the TMS0200 Building Blocks makes fully use of their possibilities like addressing up to 4 ROM chips and up to 16 Register Chips, did the design lay out the architecture of the TMC0500 Building Blocks for Scientific Calculators introduced with the "Slide Rule" calculator SR-50 in January 1974 and leading all the way to the legendary TI Programmable 59 and the amazing SR-60A Prompting Desktop calculator.

QUICK-LINK to TMS0200 Family.

Type	Calculators	Function
TMS0201	TI-4000, TI-410, Canon L121F, Canon L1210	Basic Desktop Calculator Panaplex Display
TMS0202	SR-20	Scientific Desktop Calculator Panaplex Display
TMS0203	TI-450, TI-500, TI-620, TEAL 6121D, TEAL PM1200, Elite 1202M	Basic and Printing Desktop Calculator Panaplex Display, VF-Display
TMS0206	Olympia CD401A	Basic Desktop Calculator VF-Display
TMS0207	SR-22	Hexadecimal Calculator/Converter Panaplex Display

	Description	Comments
Architecture	Building Blocks
Category	Register Processor	64-bit registers (16 digits * 4 Bits)
ROM Size	not applicable
RAM Size	256 Bits	4 Registers * 64 Bits

Parameter	Min	Typ	Max	Unit	Comments
VSS	+9.2	+10.0	+10.6	V
VDD		0		V
VGG	-7.2	-7.0	-6.4	V
PHI1, PHI2	50	250	300	kHz	Opposite phases

Pin	IO	Function	Pin	IO	Function
1	O	S-Times A	40	V	VDD (0 V)
2	O	S-Times B	39	V	VGG (-7 V)
3	O	S-Times C	38	I	Clock Input 1
4	O	S-Times D	37	I	Clock Input 2
5	O	Decimal Point	36	IO	I/O Bus I/O 8
6	O	Comma	35	IO	I/O Bus I/O 4
7	O	BCD/Binary Out 1	34	IO	I/O Bus I/O 2
8	O	BCD/Binary Out 2	33	IO	I/O Bus I/O 1
9	O	BCD/Binary Out 4	32	O	Condition Flag
10	O	BCD/Binary Out 8	31	O	Condition Flag B
11	O	Flag Overflow	30	O	Condition Flag A
12	O	Digit driver 1 (Right)	29	I	Busy
13	O	Digit driver 15 (Left)	28	I	Instruction word B6-B12
14	O	Digit driver 14	27	I	Instruction word B0-B5
15	O	Digit driver 13	26	IO	External Access
16	O	Progr. Strobe	25	I	Keymatrix input T
17	O	P Register	24	I	Keymatrix input S
18	I	Keymatrix input N	23	V	VSS (+10 V)
19	I	Keymatrix input O	22	I	Keymatrix input R
20	I	Keymatrix input P	21	I	Keymatrix input Q

If you have additions to the above datasheet please email: joerg@datamath.org.

© Joerg Woerner, March 5, 2021. No reprints without written permission.