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Texas Instruments TMC0500 Architecture

Description

Texas Instruments introduced with the "Slide Rule" calculator SR-50 in January 1974 their first product based on the TMC0500 Building Blocks for Scientific and Programmable Calculators leading all the way to the legendary TI Programmable 59 and the amazing SR-60A Prompting Desktop calculator.

The TMC0500 Building Blocks are an evolution of the TMS0200 Building Blocks for Desktop Calculators introduced already in 1973 with the TI-4000 and clearly designed with portable calculators in mind, consequently minimizing the necessary real estate of the "calculator brain":

TMS0200 - Minimum configuration: 40-pin Data Chip + 40-pin ROM Chip + 16-pin Segment Decoder, optional ROM Expansion with 40-pin ROM/Register Chip
TMC0500 - Minimum configuration: 28-pin Arithmetic Chip + 28-pin Scanning ROM Chip, optional ROM Expansion with piggy-backing a second Scanning ROM Chip and/or additional 8-pin Bare ROM Chips

The TMS0200 is based on the Register Architecture of the TMS0100 single-chip calculator circuit design introduced in September 1971 but expands its Serial-Access Memory (SAM) from 3 Registers * 13 digits to 4 Registers * 16 digits, outsources the 320*11 Bits Program Memory and display scanning to a TMS0300 ROM Chip with a capacity of 512*13 Bits and 13 digits scan outputs and abandons the integrated segment decoder.

The TMC0500 Building Blocks optimized the TMS0200 Register Architecture for Desktop Calculators with expanding its SAM from 4 Registers to 5 Registers * 16 digits, using a 10 Digits Mantissa and 2 Digits Exponent representation and doubling the Programming Memory from 512*13 Bits to 1,024*13 Bits. The task sharing between Data Chip and ROM Chip of the TMS0200 was slightly changed and the TMC0501 Arithmetic Chip does not include any keyboard or display scanning, the TMC0520 SCOM (Scanning and Read-Only Memory) Chip features a total of 16 digit outputs in addition to the 16 stored constants used with transcendental functions with 16 digits, each.

Both chip count and their real estate on the printed circuit board (PCB) was greatly reduced by various measures:

Integration of the external Segment Decoder into the TMC0501 Arithmetic Chip
Reduction of pin count from 40 pins to 28 pins with a new concept to synchronize the 16 states of the Instruction Cycle,
   dropping the IRG B line and consolidating the various Condition and Flag outputs
Novel Chip Select method for ROMs to allow piggy-backing two SCOM Chips
Introduction of TMC0560 BROM (Bare ROM with 1k*13 Bits capacity) Chips in small 8-pin packages

With the introduction of the SR-51-II in 1976 the original 28-pin DIP (Dual Inline Package) encapsulation used for the TMC0501 Arithmetic Chip was changed to 28-pin SDIP (Shrink Dual Inline Package) roughly the size of a standard 20-pin DIP encapsulation and the newly introduced TMC0580 DSCOM (Double Scanning and Read-Only Memory) more than doubled the capacity of the SCOM from 1k*13 Bits to 2.5k*13 Bits in a 28-pin SDIP housing paving the way for the TI Programmable 59.

The similarity between the TMC0500 and TMS0200 architecture allowed even the introduction of additional TMC02xx devices used with products based on the TMC0500 Building Blocks for Scientific and Programmable Calculators:

Device Description Comments
TMC0250 Printer/Display Chip Interface to Thermal Printer Mechanism and Dot-Matrix Display


One pin labeled "PFS" selects on these Chips for Thermal Printers and Dot-Matrix Displays how the 13-bit Instruction Word is provided from the ROM:

TMS0200 Mode (n.c.): IRG A Input for B0 B5 and IRG B Input for B6 B12
TMC0500 Mode: (VDD): IRG B Input for B0 B12

Communication between the TMC0501/TMC0501E Arithmetic Chips to the other family members of the TMC0500 Building Blocks is realized with multiple means:

IDLE, CLK 1 and CLK 2 Outputs are used to synchronize all peripherals connected to the TMC501/TMC0501E Arithmetic Chips with the 16 States of its Instruction Cycle
EXT Output indicates that the TMC501/TMC0501E Arithmetic Chips is addressing external memories/registers
IRG Input to receive the 13-bit Instruction Words from the TMC0520/TMC0540/TMC0560/TMC0580 ROM chips
4-bit bidirectional I/O Bus I/O 8, I/O 4, I/O 2, and I/O 1 to communicate with Multi-Register Chips and other peripherals
Various Condition and Flag Outputs to signal certain states of operations to its peripherals
BUSY Input for slow devices like the Printer Chip

Texas Instruments introduced in January 1974 with the SR-50 a product utilizing only the bare minimum of the capabilities of the TMC0500 Building Blocks for Scientific and Programmable Calculators but the subsequent introduction of the SR-52 Programmable and the PC-100 Printer Cradle clearly demonstrated the scalability of this groundbreaking architecture. While from a technology point of view the SR-60A Prompting Calculator marked the eclipse of the TMC0500 Building Blocks, was it the TI Programmable 59 that will be remembered for eternity. And the TI-58C lastly will be remembered for combining a Continuous Memory in modern CMOS technology with the PMOS technology of the TMC0501 tracing back to the Sixties before Project X converted the successor of the TI-59 into a pure CMOS design known as TI Programmable 88.

Products and Applications

All Texas Instruments scientific and programmable calculators introduced between 1974 (SR-50) and 1976 (SR-56) and the high-end models between 1977 (TI-59) and 1979 (TI-58C) adopted the TMC0500 Building Blocks for Scientific and Programmable calculators.

Integrated Circuits

Device Description Comments
TMC0501 Arithmetic Chip Register Processor with five 16-digit Registers and segment decoder/driver
TMC0501E Enhanced Arithmetic Chip Optimized for AOS
TMC0520 Scanning and Read-Only Memory Chip 1,024*13 Bits Instruction Memory with serial interface to Arithmetic Chip, 16 Constants with 16 digits, each and 16-digit display scanning
TMC0530 Scanning and Read-Only Memory Chip TMC0520 with integrated clock oscillator
TMC0540 Customer Read-Only Memory Chip 5,000*8 Bits Keycode Memory for Solid State Software Modules
TMC0560 Bare Read-Only Memory Chip 1k*13 Bits Instruction Memory with serial interface to Arithmetic Chip, 8-pin package
TMC0580 Double Scanning and Read-Only Memory Chip 2.5k*13 Bits Instruction Memory with serial interface to Arithmetic Chip, 16 Constants with 16 digits, each and 16-digit display scanning
TMC0590 Continuous Memory Interface Chip Adopts 1k*4 Bits CMOS SRAM with backup battery to Arithmetic Chip
TMC0594 Magnetic I/O Chip Four channel interface for magnetic card reader TI-59
TMC0595 Magnetic I/O Chip Four channel interface for magnetic card reader SR-52(A)
TMC0596 Magnetic I/O Chip Four channel interface for magnetic card reader SR-60(A)
TMC0598 Multi-Register Chip TMC0599 with single-voltage supply
TMC0599 Multi-Register Chip 240*8 Bits Random Access Memory with 4-bit I/O Bus to Arithmetic Chip, stores 240 program steps or 30 numbers of 16 digits, each

Architecture

  Description Comments
Architecture Building Blocks  
Category Register Processor 64-bit registers (16 digits * 4 Bits)
ROM Size 1k * 13 Bits to 8k *13 Bits SR-50 to SR-60
Register Size 320 Bits 5 Registers * 64 Bits
RAM Size 0 to tbd * 8 Bits SR-50 to SR-60A w/ Memory Opt. 3

Technical Specifications

Parameter Min Typ Max Unit Comments
VSS   0   V  
VDD2 -5.5 -5.0 -4.5 V TMC0590 only
VDD -10.5 -10.0 -9.5 V  
VGG -16.3 -15.8 -15.3 V  
PHI1, PHI2   225 230 kHz Opposite phases
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If you have additions to the above datasheet please email: joerg@datamath.org.

Joerg Woerner, March 3, 2021. No reprints without written permission.