DATAMATH CALCULATOR MUSEUM
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DATAMATH CALCULATOR MUSEUM |
Texas Instruments introduced on January 15, 1974 with the SR-50 their first "Slide Rule" calculator adding trigonometric and hyperbolic functions to the feature set of the SR-10, SR-11, and SR-16 line of calculators to compete with Hewlett Packards HP-35. The SR-50 was the first product based on the TMS0500 Building Blocks for Scientific and Programmable Calculators and used its minimum configuration combining the TMC0501 Arithmetic Chip and one TMC0521 SCOM (Scanning Read-Only Memory) Chip with the necessary display drivers for its 14-digit LED display, power supply and clock generation.
The TMC0560 BROM (Bare Read-Only Memory) Chip integrates 1,024*13 Bits Instruction Memory with serial interface to the TMC0501/TMC0501E Arithmetic Chips providing a ROM extension for the TMC0520/TMC0530 SCOM and TMC0580 DSCOM (Double SCOM) Chips used with product based on the TMS0500 Building Blocks for Scientific and Programmable Calculators.
Communication between the TMC0501E Enhanced Arithmetic Chip and the TMC0560 BROM Chip is realized with multiple means:
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IDLE, PHI 1 and PHI 2
Signals are used to synchronize all peripherals connected to the
TMC0501/TMC0501E Arithmetic Chips with the 16 States of its Instruction Cycle EXT Output indicates that the TMC0501/TMC0501E Arithmetic Chips is addressing external memories/registers IRG Input to receive the 13-bit Instruction Words from the ROM of the TMC0560 |
QUICK-LINK to
TMS0500 Family.
| Type | Products | Function |
| TMC0561 | PC-100, PC-100A, PC-100B | BROM 3 for SR-52, (SR-51) |
| TMC0562 | SR-52 | BROM 2, with TMC0524 |
| TMC0562 | SR-52A | BROM 2, with TMC0534 |
| TMC0563 | SR-52 | BROM 4, with TMC0524 |
| TMC0563 | SR-52A | BROM 4, with TMC0534 |
| TMC0564 | SR-60 | BROM 2, with TMC0526 |
| TMC0565 | SR-60 | BROM 3, with TMC0526 |
| TMC0566 | SR-60 | BROM 4, with TMC0526 |
| TMC0567 | SR-60 | BROM 5, with TMC0526 |
| TMC0568 | SR-60 | BROM 6, with TMC0526 |
| TMC0569 | PC-100, PC-100A, PC-100B | BROM 3 for SR-56 |
| TMC0570 | SR-60 (Expansion) | BROM 6, with TMC0526 |
| TMC0571 | TI-58, TI-59 | BROM 6, with TMC0582, TMC0583 |
| TMC0572 | TI-5230 | BROM 6, with TMC0587, TMC0588 |
| TMC0573 | TI-58C | BROM 6, with CD2400, CD2401 |
| Revision | Products | First Prototypes | Comments |
| TMC0561 | PC-100 | Initial design, BROM 3 for SR-52 | |
| TMC0561 Rev A | PC-100 | +, -, *, : Identity | |
| TMC0561 Rev B | PC-100 | May 1975 | |
| TMC0562 | SR-52 | Initial design, BROM 2 | |
| TMC0562 Rev A | SR-52 | April 1975 | cos-1 [-] 1, Delete and wrong 524A loc. (HLTs) |
| TMC0562 Rev B | SR-52 | June 1975 | Write 3 Checksums |
| TMC0562 Rev C | SR-52 | October 1975 | |
| TMC0563 | SR-52 | Initial design, BROM 4 | |
| TMC0563 Rev A | SR-52 | May 1975 | Memory Over-/Underflow, [P→R] |
| TMC0563 Rev B | SR-52 | June 1975 | |
| TMC0564 | SR-60 | Initial design, BROM 2 PQ13 modifications for A |
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| TMC0564 Rev A | SR-60 | March 1975 | [DMS], [HYP] [DMS] hang up, [cos-1 [-] 1 |
| TMC0564 Rev B | SR-60 | July 1975 | STP → SBR |
| TMC0564 Rev C | SR-60 | November 1975 | [sinh-1 |X| 10-6 decode |
| TMC0564 Rev D | SR-60 | March 1976 | |
| TMC0565 | SR-60 | Initial design, BROM 3 Arc SCT change for A |
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| TMC0565 Rev A | SR-60 | April 1975 | [DMS] |
| TMC0565 Rev B | SR-60 | May 1975 | (indecipherable) |
| TMC0565 Rev C | SR-60 | October 1975 | |
| TMC0566 | SR-60 | April 1975 | Initial design, BROM 4 Fix 8, [RST] or Query, Rd Spin |
| TMC0566 Rev A | SR-60 | November 1975 | |
| TMC0567 | SR-60 | Initial design, BROM 5 WR8 + H/VSUM change for A |
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| TMC0567 Rev A | SR-60 | May 1975 | VSUM Rd + Rd Spin |
| TMC0567 Rev B | SR-60 | November 1975 | |
| TMC0568 | SR-60 | April 1975 | Initial design, BROM 6 CA 599s, Lbl Tbl [-] 0 |
| TMC0568 Rev A | SR-60 | July 1975 | ./EE [LRN] |
| TMC0568 Rev B | SR-60 | November 1975 | also see TMC0570 for Expansion |
| TMC0569 | PC-100 | December 1975 | Initial design, BROM 3 for SR-56 |
| TMC0570 | SR-60 (Expansion) | June 1976 | Initial design, BROM 6 > 1920 Steps (≤ 5760) |
| TMC0571 | SR-52 II (TI-59) | December 1976 | Initial design, BROM 6 Added capability |
| TMC0571 Rev A | SR-52 II (TI-59) | January 1977 | (indecipherable) |
| TMC0571 Rev B | SR-52 II (TI-59) | March 1977 |
| BROM | Top Markings Bottom Markings |
Calculator Date Code |
Instruction ROM ©Texas Instruments |
| TMC0561 Rev B | TMC0561NL BA7604 0561 |
PC-100 LTA1776 |
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| TMC0562 Rev. C | TMC0562NL CP7609 DP0562C SINGAPORE |
SR-52 LTA1776 |
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| TMC0562 Rev. C | TMC0562NL CP7640 ● DP0562C SINGAPORE |
SR-52A LTA0777 |
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| TMC0563 Rev. B | TMC0563NL BP7605 DP0563B SINGAPORE |
SR-52 LTA1776 |
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| TMC0563 Rev. B | TMC0563NL BP7640 ● DP0563B SINGAPORE |
SR-52A LTA0777 |
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| TMC0569 | TMC0569NL A7603 0569 |
PC-100 LTA1776 |
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| TMC0571 Rev. B | TMC0571NL BP7849 D0571B SINGAPORE |
TI-59 ATA1979 |
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| TMC0573 | TMC0573NL P8018K W0573 SINGAPORE |
TI-58C ATA2980 |
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IMPORTANT NOTE: This information is provided as a service of the Datamath Calculator Museum to enthusiasts of early Texas Instruments calculators and please be aware that the Copyright of the Software transcribed in the ROM Images, the underlying algorithm or application might be owned by Texas Instruments or other third parties. The commercial use of the published Recorded ROM Images is strictly prohibited. In case of questions please contact us using the email address listed in the footer of this webpage.
| Item | Min | Typ | Max | Unit | Comments |
| VSS | 0 | V | |||
| VDD | -10.5 | -10.0 | -9.5 | V | |
| VGG | -16.3 | -15.8 | -15.3 | V | |
| PHI1, PHI2 | 225 | 230 | kHz | Opposite phases |
INSTRUCTION MEMORY
The TMC0560 BROM (Bare Read-Only Memory) integrates 1,024*13 Bits Instruction Memory with serial interface to the TMC0501/TMC0501E Arithmetic Chips providing a ROM extension for the TMC0520/TMC0530 SCOM and TMC0580 DSCOM (Double SCOM) Chips used with product based on the TMS0500 Building Blocks for Scientific and Programmable Calculators. Internal, mask-programmed Chip-Select logic allow the use of a mix of up to 8 SCOM or BROM Chips in the design. With the Arithmetic Chip fetching the first instruction after power-on from Address 0, feature all known calculator designs based on the TMS0500 Building Blocks at least one SCOM or DSCOM addressed with the CS0 signal. The innovative architecture of the TMS0500 Building Blocks allows not only the traditional loading of a ROM Address, additional logic inside the ROM addressing circuitry listens into the current instruction and based on additional signal even calculates the next ROM address. For this purpose the TMC0501/TMC0501E uses all 16 State Times S0 to S15 to communicate with its EXT Signal to the ROM Chips of the calculator:
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S0: PREG - Program
Register Signal to load the address counter with a 10-bit ROM Address S1: COND - Condition Signal to allow for conditional branches S2: HOLD - Hold Condition Signal to suppress auto-increment or decrement of the address counter S3 - S12: lower 10-bit ROM Address (LSB first) S13 - S15: upper 3-bit ROM Address (MSB last) for CS0 - CS7 |
The power-on circuitry of TMC0501/TMC0501E Arithmetic Chips transmits on the EXT Signal for a few Digit Times a logical 1 at S0 time and logical 0 thereafter, effectively loading the address counter of the SCOM/DSCOM with 0x000 and selecting the ROM responding to CS0.
The TMC0560 was manufactured in a 8 um metal gate PMOS process (metal width = 0.30 mil / 8.0 um, metal spacing = 0.35 mil / 9.0 um, diffusion width = 0.25 mil / 6.0 um, diffusion spacing = 0.30 mil / 8.0 um).
The die size of the TMC0560 is approximately 150 mils * 180 mils / 3.7 mm * 4.5 mm.
The TMC0560 uses a standard 0.3 wide 8-pin DIP (Dual In-line Package with a 0.1 / 2.54 mm lead pitch).
| Pin | IO | Function | Pin | IO | Function |
| 1 | V | Negative Voltage VGG | 8 | V | Common Voltage |
| 2 | V | Negative Voltage VDD | 7 | I | Clock Input 1 |
| 3 | O | Instruction words | 6 | I | Clock Input 2 |
| 4 | I | Calculating status | 5 | I | External access |
If you have additions to the above datasheet please email: joerg@datamath.org.
© Sean Riddle and Joerg Woerner, February 02, 2001. No reprints
without written permission.
