DATAMATH CALCULATOR MUSEUM
Texas Instruments introduced on January 15, 1974 with the SR-50 their first "Slide Rule" calculator adding trigonometric and hyperbolic functions to the feature set of the SR-10, SR-11, and SR-16 line of calculators to compete with Hewlett Packards HP-35. The SR-50 was the first product based on the TMC0500 Building Blocks for Scientific and Programmable Calculators and used its minimum configuration combining the TMC0501 Arithmetic Chip and one TMC0521 SCOM (Scanning Read-Only Memory) Chip with the necessary display drivers for its 14-digit LED display, power supply and clock generation. Later Scientific Calculators made use of the flexibility of the TMC0500 architecture by using multiple SCOMs (SR-51), adding program and data memory (SR-56) and even magnetic card readers (SR-52) and a printer and matrix display (SR-60).
All TI scientific and programmable calculators introduced between 1974 (SR-50) and 1976 (SR-56) and the high-end models between 1977 (TI-59) and 1979 (TI-58C) adopted the TMC0500 Building Blocks for Scientific and Programmable calculators:
TMC0501 Arithmetic Chip Register Processor with five 16-digit Registers and segment decoder/driver
TMC0501E Enhanced Arithmetic Chip Optimized for AOS
TMC0520 Scanning and Read-Only Memory Chip 1,024*13 Bits Instruction Memory with serial interface to Arithmetic Chip, 16 Constants with 16 digits, each and 16-digit display scanning
TMC0530 Scanning and Read-Only Memory Chip TMC0520 with integrated clock oscillator
TMC0540 Customer Read-Only Memory Chip 5,000*8 Bits Keycode Memory for Solid State Software Modules
TMC0560 Bare Read-Only Memory 1k*13 Bits Instruction Memory with serial interface to Arithmetic Chip, 8-pin package
TMC0580 Double Scanning and Read-Only Memory Chip 2.5k*13 Bits Instruction Memory with serial interface to Arithmetic Chip, 16 Constants with 16 digits, each and 16-digit display scanning
TMC0590 Continuous Memory Interface Chip Adopts 1k*4 Bits CMOS SRAM with backup battery to Arithmetic Chip
TMC0594 Magnetic I/O Chip Four channel interface for magnetic card reader TI-59
TMC0595 Magnetic I/O Chip Four channel interface for magnetic card reader SR-52
TMC0596 Magnetic I/O Chip Four channel interface for magnetic card reader SR-60
TMC0598 Multi-Register Chip TMC0599 with single-voltage supply
TMC0599 Multi-Register Chip 240*8 Bits Random Access Memory with 4-bit I/O Bus to Arithmetic Chip, stores 240 program steps or 30 numbers of 16 digits, each
The TMC0500 Building Blocks are an evolution of the TMS0200 Building Blocks for Desktop Calculators introduced already in 1973 with the TI-4000 and clearly designed with portable calculators in mind, consequently minimizing the necessary real estate of the "calculator brain":
TMS0200 - Minimum configuration: 40-pin Data Chip + 40-pin ROM Chip + 16-pin Segment Decoder, optional ROM Expansion with 40-pin ROM/Register Chip
TMC0500 - Minimum configuration: 28-pin Arithmetic Chip + 28-pin Scanning ROM Chip, optional ROM Expansion with piggy-backing a second Scanning ROM Chip and/or additional 8-pin Bare ROM Chips
The TMS0200 is based on the Register Architecture of the TMS0100 single-chip calculator circuit design introduced in September 1971 but expands its Serial-Access Memory (SAM) from 3 Registers * 13 digits to 4 Registers * 16 digits, outsources the 320*11 Bits Program Memory and display scanning to a TMS0300 ROM Chip with a capacity of 512*13 Bits and 13 digits scan outputs and abandons the integrated segment decoder.
The TMC0500 optimized the TMS0200 Register Architecture for Desktop Calculators with expanding its SAM from 4 Registers to 5 Registers * 16 digits, using a 10 Digits Mantissa and 2 Digits Exponent representation and doubling the Programming Memory from 512*13 Bits to 1,024*13 Bits. The task sharing between Data Chip and ROM Chip of the TMS0200 was slightly changed and the TMC0501 Arithmetic Chip does not include any keyboard or display scanning, the TMC0520 SCOM (Scanning and Read-Only Memory) Chip features a total of 16 digit outputs in addition to the 16 stored constants used with transcendental functions with 16 digits, each. In addition to the 5 Registers of the TMC0501 Arithmetic Chip labeled A, B, C, D, and E integrates the SCOM Chip two additional Registers with 16 digits capacity each, and named accordingly Register F and Register G .
Communication between the TMC0501/TMC0501E Arithmetic Chips to the other family members of the TMC0500 Building Blocks is realized with multiple means:
IDLE, CLK 1 and CLK 2 Outputs are used to synchronize all peripherals connected to the TMC501/TMC0501E Arithmetic Chips with the 16 States of its Instruction Cycle
EXT Output indicates that the TMC501/TMC0501E Arithmetic Chips is addressing external memories/registers
IRG Input to receive the 13-bit Instruction Words from the TMC0520/TMC0530/TMC0540/TMC0560/TMC0580 ROM Chips
4-bit bidirectional I/O Bus I/O 8, I/O 4, I/O 2, and I/O 1 to communicate with Multi-Register Chips and other peripherals
Various Condition and Flag Outputs to signal certain states of operations to its peripherals
BUSY Input for slow devices like the Printer Chip
The TMC0501 was soon replaced with the TMC0501E and only early products make us of the original design.
QUICK-LINK to TMS0500 Family.
SR-51-II, SR-60A, TI-58, TI-58C, TI-59, TI-5230
|TMC0501 Rev E||SR-52||April 1975||Marking E and/or -5
Renamed to TMC0501E
SR-52 II (TI-59)
|Shrink Plastic Dual In-line Package|
Lacking "backward compatibility" between the individual Revisions of the TMC0501 Arithmetic Chip and products using AOS relying on the Rev E of the design, Texas Instruments consequently renamed the TMC0501 Rev. E into TMC0501E Enhanced Arithmetic Chip.
|Architecture||Building Blocks||Arithmetic Chip|
|Category||Register Processor||64-bit registers (16 digits * 4 Bits)|
|ROM Size||not applicable||13-bit (8k*13) Memory Adressing|
|RAM Size||320 Bits||5 Registers * 64 Bits|
|PHI1, PHI2||225||230||kHz||Opposite phases|
The TMC0501E is manufactured in a 7.5 um metal gate PMOS process (metal width = 0.3 mil / 7.5 um, metal spacing = 0.30 mil / 7.5 um, diffusion width = 0.25 mil / 6.0 um, diffusion spacing = 0.35 mil / 9.0 um).
The die size of the TMC0501E is approximately 215 mils * 220 mils / 5.5 mm * 5.6 mm.
The TMC0501ES uses a 0.4 wide 28-pin SPDIP (Shrink Plastic Dual In-line Package with a 0.07 / 1.778 mm lead pitch, while the TMC0501 Revision E uses a standard 0.6 wide 28-pin DIP (Dual In-line Package with a 0.1 / 2.54 mm lead pitch).).
|1||O||Segment driver DP||28||O||Segment driver G|
|2||O||Segment driver B||27||V||Negative Voltage VGG|
|3||O||Segment driver A||26||V||Negative Voltage VDD|
|4||O||Segment driver F||25||IO||SCOM Interface D0|
|5||O||Segment driver C||24||IO||SCOM Interface D1|
|6||O||Segment driver D||23||IO||SCOM Interface D2|
|7||O||Segment driver E||22||IO||SCOM Interface D3|
|8||I||Keymatrix input T||21||I||Instruction words|
|9||I||Keymatrix input S||20||O||Calculating status|
|10||I||Keymatrix input R||19||O||External access|
|11||I||Keymatrix input Q||18||I||Clock Input 2|
|12||I||Keymatrix input P||17||I||Clock Input 1|
|13||I||Keymatrix input O||16||V||Common Voltage|
|14||I||Keymatrix input N||15||O||Segment driver H|
|The Segment drivers A-G and DP (Decimal Point) are connected to the display in the pictured way. The H segment is used for the negative sign of the Mantissa and computing symbol.|
The keyboards of all calculators based on the TMC0501E Arithmetic chip consist of a x/y-matrix connected to the SCOM digit driver outputs and the TMC0501E keymatrix inputs. Find the corresponding key connection within the SCOM datasheets.
Calculators based on the TMC0501E make use of a 12-digit LED-display with common cathode architecture. The TI-58 and TI-59 use the LED-stick xxx. The segments are driven directly from the TMC0501E, the digits use external drivers (SN27882) connected to the corresponding DSCOM chip.
If you have additions to the above datasheet please email: email@example.com.
© Joerg Woerner, March 26, 2021. No reprints
without written permission.