DATAMATH  CALCULATOR  MUSEUM

Texas Instruments TMC0520 SCOM (Scanning and Read-Only Memory) Chip

• Features

Texas Instruments introduced on January 15, 1974 with the SR-50 their first "Slide Rule" calculator adding trigonometric and hyperbolic functions to the feature set of the SR-10, SR-11, and SR-16 line of calculators to compete with Hewlett Packard’s HP-35. The SR-50 was the first product based on the TMC0500 Building Blocks for Scientific and Programmable Calculators and used its minimum configuration combining the TMC0501 Arithmetic Chip and one TMC0521 SCOM (Scanning Read-Only Memory) Chip with the necessary display drivers for its 14-digit LED display, power supply and clock generation. Later Scientific Calculators made use of the flexibility of the TMC0500 architecture by using multiple SCOMs (SR-51), adding program and data memory (SR-56) and even magnetic card readers (SR-52) and a printer and matrix display (SR-60).

The TMC0520 SCOM Chip integrates 1,024*13 Bits Instruction Memory with serial interface to the TMC0501 Arithmetic Chip/TMC0501E Enhanced Arithmetic Chip, 16 Constants mainly used for the calculation of transcendental functions with 16 digits, each accessible through a 4-bit bidirectional I/O bus and outputs for 16-digit display scanning. In addition to the 5 Registers of the TMC0501/TMC0501E labeled A, B, C, D, and E integrates the SCOM Chip two additional Registers with 16 digits capacity each, and named accordingly Register F and Register G. While the design of the TMC0520 SCOM Chip would allow to use up to 8 devices in one product, were most designs implemented with additional TMC0560 BROM (Bare Read-Only Memory) Chips to increase program memory capacity.

Communication between the TMC0501 Arithmetic Chip/TMC0501E Enhanced Arithmetic Chip and the other family members of the TMC0500 Building Blocks is realized with multiple means:

• IDLE, CLK 1 and CLK 2 Outputs are used to synchronize all peripherals connected to the TMC0501/TMC0501E Arithmetic Chips with the 16 States of its Instruction Cycle
• EXT Output indicates that the TMC0501/TMC0501E Arithmetic Chips is addressing external memories/registers
• IRG Input to receive the 13-bit Instruction Words from the ROM of the TMC0520
• 4-bit bidirectional I/O Bus I/O 8, I/O 4, I/O 2, and I/O 1 to communicate with registers

The TMC0520 SCOM Chip was replaced in 1976 with the TMC0530 SCOM Chip adding an additional two-phase clock generator as a bond-out option with a 30-pin DIP (Dual Inline Package) encapsulation used only with the SR-52A.

QUICK-LINK to TMS0500 Family.

• Family Members and Applications

Type Calculators Function
TMC0521 SR-50, SR-50A SCOM 1
TMC0522 SR-51, SR-51A SCOM 1
TMC0523 SR-51, SR-51A SCOM 2
TMC0524 SR-52 SCOM 1, with TMC0562, TMC0563
TMC0526 SR-60 SCOM 1, with TMC0564, TMC0565, TMC0566, TMC0567, TMC0568/TMC0570

• Revisions

Revision Products First Prototypes Comments
TMC0521 SR-50   Initial design
TMC0521 Rev A SR-50    
TMC0521 Rev B SR-50   Marking B and/or -2
Forensics: 9.00000527288
TMC0521 Rev C SR-50   Marking C and/or -4
Forensics: 9.00000527288
TMC0521 Rev D SR-50 July 1974 Marking D and/or -5
Forensics: 9.000004661314
TMC0521 Rev E SR-50, SR-50A April 1975 Marking E and/or -5
Forensics: 9.000004661314
TMC0522
TMC0523
SR-51   Initial design, SCOM 1
Initial design, SCOM 2
TMC0522 Rev A
TMC0523 Rev A
SR-51    
TMC0522 Rev B
TMC0523 Rev B
SR-51    
TMC0522 Rev C
TMC0523 Rev C
SR-51    
TMC0522 Rev A5
TMC0523 Rev A5
SR-51A   Marking A and -5
TMC0524 SR-52 (February 1975) Initial design, SCOM 1
TMC0524 Rev A SR-52 April 1975 Implied Multiplication removed
TMC0524 Rev B SR-52 August 1975 Replaced by TMC0534
TMC0526 SR-60 April 1975 Initial design, SCOM 1
Implied Multiplication removed
AUX, BST, INS
TMC0526 Rev A SR-60 October 1975 Implied Multiplication removed


The early ROM-Codes TMC0521-2 and -4 are less accurate and was replaced in July 1974 with the TMC0521-5 ROM-Code. Please learn more about Calculator forensics.

• Technical Specifications

Parameter Min Typ Max Unit Comments
VSS   0   V  
VDD -10.5 -10.0 -9.5 V  
VGG -16.3 -15.8 -15.3 V  
PHI1, PHI2   225 230 kHz Opposite phases

• Technology

The TMC0520 is manufactured in a 7.5 um metal gate PMOS process (metal width = 0.3 mil / 7.5 um, metal spacing = 0.30 mil / 7.5 um, diffusion width = 0.25 mil / 6.0 um, diffusion spacing = 0.35 mil / 9.0 um).

• Packaging

The TMC0520 uses a standard 0.6” wide 28-pin DIP (Dual In-line Package with a 0.1” / 2.54 mm lead pitch).

• Pin Configuration

Pin IO Function Pin IO Function
1 O Digit driver 15 28 O Digit driver 14
2 V Negative Voltage VGG 27 O Digit driver 13 (OVER)
3 V Negative Voltage VDD 26 O Digit driver 12 (E-MSD)
4 IO SCOM Interface D0 25 O Digit driver 11
5 IO SCOM Interface D1 24 O Digit driver 10
6 IO SCOM Interface D2 23 O Digit driver 9
7 IO SCOM Interface D3 22 O Digit driver 8
8 O Instruction words 21 O Digit driver 7
9 I Calculating status 20 O Digit driver 6
10 I External access 19 O Digit driver 5
11 I Clock Input 2 18 O Digit driver 4
12 I Clock Input 1 17 O Digit driver 3 (M-LSD)
13 V Common Voltage 16 O Digit driver 2 (E-MSD)
14 O Digit driver 0 15 O Digit driver 1 (E-LSD)


• Keyboard Scan-Matrix

The keyboards of all calculators based on the TMC0501 Arithmetic chip consist of a x/y-matrix connected to the SCOM digit driver outputs and the TMC0501 keymatrix inputs.

Example for the original SR-50: 

  KN KO KP KQ KR KS KT
D0              
D1 1 = C log   eX SUM
D2 2 - hyp        
D3 3 + . X2   D/R  
D4 4   arc     lnX  
D5 5            
D6 6 : CE 1/X   cos STO
D7 7 * +/-     sin PI
D8 8           RCL
D9 9           X<>Y
D10 0 XsqrY          
D11   XY          
D12       sqrX      
D13     EE X!   tan  

Comments: The R-D switch is detected with a diode between D14 - KT.

horizontal rule

If you have additions to the above datasheet please email: joerg@datamath.org.

© Joerg Woerner, February 02, 2001. No reprints without written permission.