DATAMATH CALCULATOR MUSEUM
Texas Instruments introduced on January 15, 1974 with the SR-50 their first "Slide Rule" calculator adding trigonometric and hyperbolic functions to the feature set of the SR-10, SR-11, and SR-16 line of calculators to compete with Hewlett Packard’s HP-35. The SR-50 was the first product based on the TMC0500 Building Blocks for Scientific and Programmable Calculators and used its minimum configuration combining the TMC0501 Arithmetic Chip and one TMC0521 SCOM (Scanning Read-Only Memory) Chip with the necessary display drivers for its 14-digit LED display, power supply and clock generation. Later Scientific Calculators made use of the flexibility of the TMC0500 architecture by using multiple SCOMs (SR-51), adding program and data memory (SR-56) and even magnetic card readers (SR-52) and a printer and matrix display (SR-60).
The Large Scale Integrated Circuits of the TMC0500 Building Blocks – like the TMS0200 Building Blocks for 12-digit Desktop and Printing calculators – were designed in a PMOS (P-channel Metal–oxide Semiconductor) process and require an external two-phase non-overlapping clock generator.
With the accuracy of the clock frequency for an electronic calculator not relevant, the first designs were based on a free-running multivibrator running during calculations at typically 250 kHz and applied to the CLK 1 and CLK 2 inputs of the PMOS chips. To lower the average power consumption of the calculator, during stand by operation (idle mode) the frequency is decreased to typically to around 80 kHz.
Requirements for the tolerance of the clock frequency applied to CLK 1 and CLK 2 inputs of the TMC0500 Building Blocks changed with the introduction of the SR-52 Programmable Calculator dramatically to ensure compatibility with one calculator writing magnetic cards and another device reading them. Texas Instruments had to control both motor speed of the four-track magnetic card read/write mechanism and data rate to and from the magnetic pick-up head very tightly due to the lack of any clocking pattern to synchronize the data at different rates.
The electronics of the SR-52 replaced the transistor-based, free-running multivibrator of the SR-50 with a more accurate design based on a mechanical resonator made of high-stability piezoelectric lead zirconate titanate (PZT). When connected to an electronic oscillator circuit, resonant mechanical vibrations in the device generate an oscillating signal of a specific frequency. Like the similar quartz crystal, they are used in oscillators for purposes such as generating the clock signal used to control timing in computers and other digital logic devices, or generating the carrier signal in analog radio transmitters and receivers.
The clock for the SR-52 PMOS chips is generated by the SN97211 Clock Generator Chip manufactured in bipolar technology with a ceramic resonator operating at a frequency of 384 kHz ± 1% and divided by two to produce a 192 kHz ± 1% two-phase clock with a 20% downtime. The TP0190N Clock Buffer Chip (actually a CD4011A Quad 2 Input NAND Gate specified for a supply voltage of 15.8 Volts) manufactured in CMOS technology conditions the signals to the proper levels of the TMC0500 Building Blocks.
The SN97211 Clock Generator Chip was retired with the introduction of the SR-52A using the TMC0534 SCOM Chip with an integrated two-phase clock generator as a bond-out option.
|PHI1, PHI2||192 ± 1%||kHz||Opposite phases|
The SN97211 was manufactured in a Bipolar process.
The SN97211 uses a standard 0.3” wide 8-pin DIP (Dual In-line Package with a 0.1” / 2.54 mm lead pitch).
|1||V||Common Voltage||8||V||Negative Voltage VGG|
|2||O||Clock Output 1||7||A||PTZ Resonator 2|
|3||V||Negative Voltage VGG||6||A||PTZ Resonator 1|
|4||O||Clock Output 2||5||V||Negative Voltage VBAT|
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© Joerg Woerner, March 23, 2021. No reprints
without written permission.